*** scsp.c	Fri Jun 24 23:32:28 2011
--- scsp.c	Sat Sep 18 21:33:44 2010
***************
*** 175,180 ****
  	u32	finc;			// phase step adder
  	u32	finct;		// non ajusted phase step
  
  	s32	ecnt;			// enveloppe counter
  	s32	einc;			// enveloppe current step adder
  	s32	einca;		// enveloppe step adder for attack
--- 175,181 ----
  	u32	finc;			// phase step adder
  	u32	finct;		// non ajusted phase step
  
+ #ifndef GEKKO // to avoid crash.
  	s32	ecnt;			// enveloppe counter
  	s32	einc;			// enveloppe current step adder
  	s32	einca;		// enveloppe step adder for attack
***************
*** 182,187 ****
  	s32	eincs;		// enveloppe step adder for decay 2
  	s32	eincr;		// enveloppe step adder for release
  	s32	ecmp;			// enveloppe compare to raise next phase
  	u32	ecurp;		// enveloppe current phase (attack / decay / release ...)
  
  	void	(*enxt)(struct slot_t *);	// enveloppe function pointer for next phase event
--- 183,197 ----
  	s32	eincs;		// enveloppe step adder for decay 2
  	s32	eincr;		// enveloppe step adder for release
  	s32	ecmp;			// enveloppe compare to raise next phase
+ #else
+ 	u32	ecnt;			// enveloppe counter
+ 	u32	einc;			// enveloppe current step adder
+ 	u32	einca;		// enveloppe step adder for attack
+ 	u32	eincd;		// enveloppe step adder for decay 1
+ 	u32	eincs;		// enveloppe step adder for decay 2
+ 	u32	eincr;		// enveloppe step adder for release
+ 	u32	ecmp;			// enveloppe compare to raise next phase
+ #endif
  	u32	ecurp;		// enveloppe current phase (attack / decay / release ...)
  
  	void	(*enxt)(struct slot_t *);	// enveloppe function pointer for next phase event
***************
*** 397,402 ****
  
  static void scsp_dma(void)
  {
  	if (scsp.dmfl & 0x20)
  	{
  		// dsp -> scsp_ram
--- 407,413 ----
  
  static void scsp_dma(void)
  {
+ #ifdef SCSP_DEBUG
  	if (scsp.dmfl & 0x20)
  	{
  		// dsp -> scsp_ram
***************
*** 407,412 ****
  		// scsp_ram -> dsp
                  SCSPLOG("scsp dma: scsp_ram(%08lx) -> reg(%08lx) * %08lx\n", scsp.dmea, scsp.drga, scsp.dmlen);
  	}
  
  	scsp_ccr[0x16 ^ 3] &= 0xE0;
  
--- 418,424 ----
  		// scsp_ram -> dsp
                  SCSPLOG("scsp dma: scsp_ram(%08lx) -> reg(%08lx) * %08lx\n", scsp.dmea, scsp.drga, scsp.dmlen);
  	}
+ #endif
  
  	scsp_ccr[0x16 ^ 3] &= 0xE0;
  
***************
*** 994,1005 ****
  
  static void scsp_set_b(u32 a, u8 d)
  {
  //      if (a != 0x41D) SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
          if ((a != 0x408) && (a != 0x41D))
  	{
  		SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
  	}
  //      SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
  
  	scsp_ccr[a ^ 3] = d;
  
--- 1006,1019 ----
  
  static void scsp_set_b(u32 a, u8 d)
  {
+ #ifdef SCSP_DEBUG
  //      if (a != 0x41D) SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
          if ((a != 0x408) && (a != 0x41D))
  	{
  		SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
  	}
  //      SCSPLOG("scsp : reg %.2X = %.2X\n", a & 0x3F, d);
+ #endif
  
  	scsp_ccr[a ^ 3] = d;
  
***************
*** 1163,1173 ****
  
  static void scsp_set_w(u32 a, u16 d)
  {
          if ((a != 0x418) && (a != 0x41A) && (a != 0x422))
  	{
  		SCSPLOG("scsp : reg %.2X = %.4X\n", a & 0x3E, d);
  	}
  //      SCSPLOG("scsp : reg %.2X = %.4X\n", a & 0x3E, d);
  
  	*(u16 *)&scsp_ccr[a ^ 2] = d;
  
--- 1177,1189 ----
  
  static void scsp_set_w(u32 a, u16 d)
  {
+ #ifdef SCSP_DEBUG
          if ((a != 0x418) && (a != 0x41A) && (a != 0x422))
  	{
  		SCSPLOG("scsp : reg %.2X = %.4X\n", a & 0x3E, d);
  	}
  //      SCSPLOG("scsp : reg %.2X = %.4X\n", a & 0x3E, d);
+ #endif
  
  	*(u16 *)&scsp_ccr[a ^ 2] = d;
  
***************
*** 1287,1292 ****
  {
  	a &= 0x3F;
  
  //      if (a != 0x21) SCSPLOG("r_b scsp : reg %.2X\n", a);
          if ((a != 0x09) && (a != 0x21))
  	{
--- 1303,1309 ----
  {
  	a &= 0x3F;
  
+ #ifdef SCSP_DEBUG
  //      if (a != 0x21) SCSPLOG("r_b scsp : reg %.2X\n", a);
          if ((a != 0x09) && (a != 0x21))
  	{
***************
*** 1294,1299 ****
  	}
  //      if (a == 0x09) SCSPLOG("r_b scsp 09 = %.2X\n", ((scsp.slot[scsp.mslc].fcnt >> (SCSP_FREQ_LB + 12)) & 0x1) << 7);
  //      SCSPLOG("r_b scsp : reg %.2X\n", a);
  
  	switch(a){
  
--- 1311,1317 ----
  	}
  //      if (a == 0x09) SCSPLOG("r_b scsp 09 = %.2X\n", ((scsp.slot[scsp.mslc].fcnt >> (SCSP_FREQ_LB + 12)) & 0x1) << 7);
  //      SCSPLOG("r_b scsp : reg %.2X\n", a);
+ #endif
  
  	switch(a){
  
***************
*** 1342,1351 ****
  {
  	a = (a >> 1) & 0x1F;
  
          if (a != 0x10)
  	{
  		SCSPLOG("r_w scsp : reg %.2X\n", a * 2);
  	}
  
  	switch(a){
  
--- 1360,1371 ----
  {
  	a = (a >> 1) & 0x1F;
  
+ #ifdef SCSP_DEBUG
          if (a != 0x10)
  	{
  		SCSPLOG("r_w scsp : reg %.2X\n", a * 2);
  	}
+ #endif
  
  	switch(a){
  
***************
*** 2375,2384 ****
  
  void FASTCALL scsp_w_w(u32 a, u16 d)
  {
  	if (a & 1)
  	{
                  SCSPLOG("ERROR: scsp w_w misaligned : %.8X\n", a);
  	}
  
  	a &= 0xFFE;
  
--- 2395,2406 ----
  
  void FASTCALL scsp_w_w(u32 a, u16 d)
  {
+ #ifdef SCSP_DEBUG
  	if (a & 1)
  	{
                  SCSPLOG("ERROR: scsp w_w misaligned : %.8X\n", a);
  	}
+ #endif
  
  	a &= 0xFFE;
  
***************
*** 2415,2424 ****
  
  void FASTCALL scsp_w_d(u32 a, u32 d)
  {
  	if (a & 3)
  	{
                  SCSPLOG("ERROR: scsp w_d misaligned : %.8X\n", a);
  	}
  
  	a &= 0xFFC;
  
--- 2437,2448 ----
  
  void FASTCALL scsp_w_d(u32 a, u32 d)
  {
+ #ifdef SCSP_DEBUG
  	if (a & 3)
  	{
                  SCSPLOG("ERROR: scsp w_d misaligned : %.8X\n", a);
  	}
+ #endif
  
  	a &= 0xFFC;
  
***************
*** 2485,2494 ****
  
  u16 FASTCALL scsp_r_w(u32 a)
  {
  	if (a & 1)
  	{
                  SCSPLOG("ERROR: scsp r_w misaligned : %.8X\n", a);
  	}
  
  	a &= 0xFFE;
  
--- 2509,2520 ----
  
  u16 FASTCALL scsp_r_w(u32 a)
  {
+ #ifdef SCSP_DEBUG
  	if (a & 1)
  	{
                  SCSPLOG("ERROR: scsp r_w misaligned : %.8X\n", a);
  	}
+ #endif
  
  	a &= 0xFFE;
  
***************
*** 2518,2527 ****
  
  u32 FASTCALL scsp_r_d(u32 a)
  {
  	if (a & 3)
  	{
                  SCSPLOG("ERROR: scsp r_d misaligned : %.8X\n", a);
  	}
  
  	a &= 0xFFC;
  
--- 2544,2555 ----
  
  u32 FASTCALL scsp_r_d(u32 a)
  {
+ #ifdef SCSP_DEBUG
  	if (a & 3)
  	{
                  SCSPLOG("ERROR: scsp r_d misaligned : %.8X\n", a);
  	}
+ #endif
  
  	a &= 0xFFC;
  
***************
*** 2687,2697 ****
  		scsp_null_rate[i - 64] = 0;
  	}
  
  	for(i = 0; i < 96; i++)
  	{
                  SCSPLOG("attack rate[%d] = %.8X -> %.8X\n", i, scsp_attack_rate[i], scsp_attack_rate[i] >> SCSP_ENV_LB);
                  SCSPLOG("decay rate[%d] = %.8X -> %.8X\n", i, scsp_decay_rate[i], scsp_decay_rate[i] >> SCSP_ENV_LB);
  	}
  
          for(i = 0; i < 256; i++)
             scsp_tl_table[i] = scsp_round(pow(10, ((double)i * -0.3762) / 20) * 1024.0);
--- 2715,2727 ----
  		scsp_null_rate[i - 64] = 0;
  	}
  
+ #ifdef SCSP_DEBUG
  	for(i = 0; i < 96; i++)
  	{
                  SCSPLOG("attack rate[%d] = %.8X -> %.8X\n", i, scsp_attack_rate[i], scsp_attack_rate[i] >> SCSP_ENV_LB);
                  SCSPLOG("decay rate[%d] = %.8X -> %.8X\n", i, scsp_decay_rate[i], scsp_decay_rate[i] >> SCSP_ENV_LB);
  	}
+ #endif
  
          for(i = 0; i < 256; i++)
             scsp_tl_table[i] = scsp_round(pow(10, ((double)i * -0.3762) / 20) * 1024.0);
